Peak value measuring and regulating circuit

ABSTRACT

The present peak value measuring and regulating circuit arrangement includes at least one maximum signal memory and one minimum signal memory for storing oscillation representing signals for a constant length of storage time (t1) during which logic circuit means controlled by the upper signal value or by the lower signal value actuate a timer which closes signal path means to supply either differential signals or actual signals representing certain load conditions to evaluating and regulating means for an evaluating time duration ( Delta t) which is independent of the frequency of said oscillation. At the end of the storage time (t1) the timer erases the stored information.

United States Patent 1191 Wawra et al.

[ Oct. 30, 1973 PEAK VALUE MEASURING AND 3,116,458 12/1963 Margopoulos328/151 x REGULATING CIRCUIT [75] Inventors: Carl-Martin Wawra, 53 m g rzazworsky Bensheim-Auerbach; Ivan Chudey, omey asse Ober-Ramstadt, bothof Germany [57] ABSTRACT [73] Ass1gnee: Carl Schenek Maschinenfabrik Thepresent peak value measurlng and regulatmg c1r- GmbH, Darmstadt, Germanycurt arrangement mcludes at least one maxlmum s1g- [22] Filed: Mar. 27,1972 nal memory and one minimum signal memory for storing oscillationrepresenting signals for -a constant [211 App! 23843l length of storagetime (t1) during which logic circuit means controlled by the uppersignal value or by the [52] U.S. Cl. 328/151, 307/235 A w r signal valueactuate a timer which closes signal [51] Int. Cl. H03]: 5/00 path meansto supply either difi'erential signals or ac- [58] Field of Search328/151; 307/235 A; tual signals repre enting certain load condition t324/103 P; 73/885 evaluating and regulating means for an evaluating timeduration (At) which is independent of the frequency [56] ReferencesCited of said oscillation. At the end of the storage time (:1)

UNITED STATES PATENTS the timer erases the stored information.

3,049,380 7/1962 Brennan 328/151 X 4 Claims, 3 Drawing Figures AA (3iCOMPARATOR EVALUATOR fAi - 38 i i 1 AM 36 I 24 COMPARATOR o EVALUATOR 4253 f I TRIGGER l 32 I 49 1 S OL 4 48 33 46 TRIGGER 54 FLOP UL 0 V 44 3417 TRIGGER 3 3O TRIGGER 29 4/ 40 a 'ot nor #27 COMPUTER 5%'$ %QMAX-LEMOHRI AMPLIFIER UL UL MIN MEMORY S PEAK VALUE MEASURING ANDREGULATING CIRCUIT BACKGROUND OF THE INVENTION The present inventionrelates to a peak value measuring and regulating circuit arrangement,more specifically, to a circuit arrangement for ascertaining the maximumand minimum values of an oscillation represented by an electrical signalto be regulated. For this purpose peak value voltage storage means areprovided. The present circuit arrangement is especially suitable for usein connection with a peak value computer in a dynamic testing machineand for controlling or regulating such testing machine.

In one prior art peak value computer circuit means are provided forforming an enveloping function for the maximum values and anotherenveloping function for the minimum values. These enveloping functionsare formed from the oscillation which is present in the form of anelectrical signal voltage. Two peak value memory or storage means areprovided for the formation of each enveloping function. These memoriesstore alternately a maximum and a minimum value which values aresupplied to the output of the circuit arrangement by means of logiccircuits comprising comparators, flipflops, AND-gates as well asOR-gates.

The known circuit arrangement is relatively involved and accordinglyexpensive. Moreover the amplifiers in the two peak voltage memories havedifi'erent drifts due to which a certain inexactness in the measuredresults cannot be avoided.

OBJECTS OF .THE INVENTION In view of the foregoing it is the aim of theinvention to achieve the following objects singly or in combina-. tion:

to avoid the drawbacks of the prior art, especially to reduce the numberof circuit elements;

to avoid the formation of an envelop function; and

to indirectly measure the actual peak or extreme values. Extreme valuesare intended to include peak values in the positive and negative sense,that is, they include maximum as well as minimum peakvalues.

SUMMARY OF THE INVENTION The above objects have been achieved accordingto the invention in a circuit arrangement comprising peak voltagestorage means, especially for peak value computers in a dynamic testingmachine, wherein two actual extreme values such as an actual extremeoscillation amplitude value and an actual extreme mean force value, arestored for a constant storage time (t1) which corresponds to one halfcycle duration at the most, wherein during said storage time said actualextreme values are supplied, after the occurrence of an extreme value,to respective evaluating means for a constant evaluation time A t) whichcannot be influenced by the frequency of said oscillation, and whereinsaid storage means are erased after the expiration of said storage time.

According to an especially advantageous feature of the invention,regulating circuit means are provided in which the actual extreme valuesare compared'with rated extreme values and wherein the resultingdifferential values are supplied to evaluating circuit means.

As compared to the above mentioned prior art circuit arrangement, thecircuit arrangement according to the invention requires practically onlyone half of the storage means required by the known circuit. Anotheradvantage of the circuit arrangement according to the invention is seenin that a higher accuracy is achieved according to the invention than bythe known circuit arrangement due to the comparison of the extremeactual values with the rated extreme values and due to the further useof the difference values for regulating purposes.

The circuit arrangement according to the invention comprises a timer forproducing the pulse for supplying the actual extreme values or thedifference values to an evaluating means and for producing the pulse forerasing the peak voltage storage means. Advantageously, such timer istriggered by logic circuit means subsequent to a maximum or a minimum.These logic circuit means comprise trigger stages connected through anAND-gate with a flip-flop which controls the generation of the time ortrigger signal.

BRIEF FIGURE DESCRIPTION In order that the invention may be clearlyunderstood, it will nowbe described, by way of example, with referenceto the accompanying drawings, wherein:

FIG. 1 illustrates a block circuit diagram of a circuit arrangementaccording to the invention for measuring and regulating the extremevalues in a dynamic material testing apparatus;

FIG. 2 illustrates a wave form diagram for explaining the operation ofthe circuit arrangement according to FIG. 1 when an intermediate storageor memory is employed; and

FIG. 3 is a wave form diagram similar to that of FIG. 2 but illustratingthe operation without the use of an intermediate memory.

DETAILED DESCRIPTION OF AN EXAMPLE EMBODIMENT FIG. 1 shows a materialtesting apparatus for producing dynamic loads applied to a test sample 1which is arranged between a frame structure 3 and a mass 4 whereby aforce measuring gauge 2 known as such is located between the test sample1 and the frame structure 3. The mass 4 is arranged opposite the forcemeasuring gauge 2. The mass is connected to the piston rod 5 of thepiston 6 located in a so called mean force or pre-load cylinder 7. Thepiston 6 may be subjected to hydraulic pressure on one or the other ofits surfaces. The piston rod 5 is connected with the further piston rod9 of the piston 10 located in an oscillating or alternating loadcylinder 11. If necessary, it is possible to arrange between. the pistonrod 5 and the piston rod 9 an intermediate transmitting element. Thecylinders 7 and 11 are also secured to the frame structure 3.

A hydraulic pressure source (not shown) supplies the cylinder 11 withhydraulic pressure through the hydraulic conduits 13 in which there isarranged a hy draulic servo valve 14 and a hydraulic switching orcontrol valve 15 whereby the supply of pressure medium is accomplishedin such a manner that the piston 10 is Y alternately subjected topressure on its upper side and on its lower side. Thus, a predeterminedoscillating load is applied to the test sample 1.

' A programming device (not shown) supplies to an input terminal 12 anamplitude rated value As. This value is compared in a comparator 19 withthe actual amplitude value Ai which is supplied to the comparator 19through the conductor 31. The value Ai as pointed out in DeutscheIndustrie Normen 50100, January, 1953, is equal to one half of thedifference between the maximum and minimum values of the oscillation.The resulting difference value AA is supplied to an evaluating means 39,such as a memory, through a switching means 37. According to theinvention, the difference value AA may pass to the evaluating means 39only during a predetermined time interval At as controlled by a timingdevice 33. The timing device 33, as will be apparent from the followingdisclosure, may be a monostable multivibrator.

Incidentally, the switch 37 which is shown, for simplicitys sake, as amechanical switching member will preferably comprise electronicswitching means. This applies also to the switch 36 to be describedbelow. Electronic switching means capable of handling the shortswitching times here involved are well known in the art.

The pulse produced by the timing device 33 for closing the signal pathis independent of the frequency of the respective oscillation so thatthe evaluation time At during which the signal path is closed is alsoindependent of the frequency. Accordingly, a signal independent of theoscillation frequency is supplied to the evaluating means 39 forregulating the hydraulic cylinder 11. If desired, an amplifier 17 may beconnected between the solenoid of the servo valve 14 and the output ofthe evaluating means 39.

A pre-load or mean force may be super-imposed over the dynamic loadproduced by the cylinder 11. Incidentally, the dynamic load oscillatesabout a zero point or value. In order to super-impose said mean loadonto the dynamic load, the piston 6 of the pre-load cylinder 7 issubjected on one of its two surfaces with hydraulic liquid establishinga predetermined constant pressure or a relatively slowly varyingpressure. For this purpose the cylinder 7 is provided at its ends withinflow and outflow openings 18 for the hydraulic fluid or liquid. Theseopenings 18 areconnected to the source of hydraulic pressure byhydraulic conduits 21 and a hydraulic servo valve 23. The hydraulicservo valve 23 is controlled or regulated by the amplifier 24 in such amanner that the desired mean force or load is established.

The programming device (not shown supplies the rated mean load value Msto an input terminal 16 of a comparator 20. The mean load or force valueMs is compared in the comparator with a mean force actual value Mi whichis supplied to the comparator 20 through the conductor 30. The value Mias further pointed out in the above noted Deutsche'lndustrie NormenSOIOO, is equal to one half of the sum of the maximum and minimum valuesof the oscillation. A differ ence value AM which may occur is suppliedto an evaluating device 38 when the switch 36 is closed. As mentionedabove, the switch 36 is closed by the timing device 33 through theconductor 35 whereby it should be noted that the switch 36 willgenerally be an electronic switch. The evaluating device 38 which mayalso bea memory device, supplies a regulating or control signalpreferably through an amplifier 24 to the solenoid of the servo valve23.

Since the piston 6 performs rapid oscillating movements in response tothe dynamic load cylinder 11, the cylinder volume on both sides of thepiston 6 is rapidly changed during each oscillating movement. It is notpossible to accommodate such a rapid equalization of the hydraulicliquid through the conduits 21. Therefore, hydraulic storage means 26are connected to respective ports 25 at the ends of the cylinder 6.These hydraulic storage means 26 take up the volume of the hydraulicfluid which is temporarily displaced by the oscillating movements of thepiston 6. The force measuring gauge 2 which produces as indicated bymeans of stress measuring strips a resistance variation proportional tothe force, is connected to a measuring amplifier 22 which in turnproduces at its output a signal voltage S proportional to the force. Theoutput of the measuring amplifier 22 is connected to a maximum andminimum voltage memory 27. This memory 27 comprises two separate storagedevices, one for the upper load; namely, the maximum amplitude and onefor the lower load; namely, the minimum load amplitude. The ascertainedmeasuring values for the upper and lower load are supplied to anintermediate memory 28 through the conductors 40 connecting the outputof the memory 27 to the input of the memory 28. The intermediate memory28 is connected to a computer 29 through conductors 41. The computer 29calculates from the upper and lower load the actual mean force value Mias well as the actual amplitude value Ai. The computer 29 may thuscomprise a pair of conventional operational amplifier circuits connectedto produce the outputs Ai =OL-UL,/2 and Mi=OL+UL./2 These values Mi andAi are supplied to the respective comparators 19 and 20 through theconduits 31 and 30 respectively.

The signal voltage S appearing at the output of the measuring amplifier22 is supplied to trigger stages 42 to 45 by means of the conductor 50.Further, the signal OL representing the upper load and occurring at oneoutput of the peak voltage storage means 27 is supplied through theconductor 51 to the trigger stages 42 and 43. The signal UL representingthe lower load is supplied through the conductor 52 to the triggerstages 44 and 45. The trigger stage 42 is so adjusted that it produces asignal at its output when the signal voltage S is smaller than thesignal OL representing the upper load. The trigger stage 43 on the otherhand is so adjusted that it produces an output signal when the signalvoltage S is larger than the signal OL representing the upper load. Thetrigger stage 44 is adjusted so that it produces an output signal whenthe signal voltage S is smaller than the signal UL representing thelower load. The trigger stage 45 is so adjusted that it produces anoutput signal when the signal voltage S is larger than the signal ULrepresenting the lower load. The output terminals of the upper loadtrigger stages 42, 43 are connected to the two inputs of a negatingAND-gate 46. In the same manner, the output terminals of the lower loadtrigger stages 44 and 45 are connected to the inputs of a furthernegating AND-gate 47. The output terminals of the AND-gates 46 and 47are connected to the two inputs of a flip-flop stage 48.

The just described logic circuit arrangement operates as follows. Thenegating AND-gate 46 can provide a voltage at its output only if zeropotential is applied to both of its negating input stages. This is thecase when the signal voltage S corresponds to the upper load signal 0Lappearing at the output of the peak voltage storage or memory 27. Inthis instance a voltage is applied to the upper input of the flip-flop48 and a signal occurs at the output 54 of the flip-flop 48. As soon asthe signal voltage S becomes smaller than the upper load signal 0Lstored in the peak voltage memory 27, the trigger stage 42 flips andapplies a voltage to its output. This signal at the output of thetrigger stage 42 is thus supplied through the conductor 53 to theANDgate 49. As a result, both input conductors 53 and 54 supply an inputsignal to the AND-gate 49 whereby the AND- gate supplies a triggersignal to the timer 33 through the conductor 32. Thus, the timer 33 isswitched on.

As soon as the signal voltage S corresponds to the lower load signal ULno voltage or signal is present at the outputs of the trigger stages 44and 45. As a result the negating AND-gate 47 responds to this conditiondue to its two negating input stages whereby a signal is supplied to thelower input of the flip-flop stage 48 which now removes the signal orvoltage from its output 54 and applies an output signal to the outputconductor 55. If the trigger stage 42 now should switch, no pulse willbe supplied for the triggering of the timer 33. The just described logiccircuit arrangement assures that the timer 33 is triggered after theoccurrence of a maximum. However, it is possible to also trigger a timerafter the occurrence of a minimum. For this purpose the output of thetrigger stage 45 and the output 55 of the flip-flop 48 would beconnected to an AND-gate similar to AND-gate 49 which would be connectedwith its output to such minimum responsive timer.

The timer 33 supplies, after a short duration of time, a pulse havingthe duration At through the conductor 35 to the switches 36 and 37. As aresult, the comparators l9 and are connected to the respectiveregulating means 39 and 38 during the time At which time At isindependent of the respective or instantaneous load frequency. The timer33 is further connected through a conductor 34 to erasing inputs of thememories 27 and 28 whereby the content of these memories may be erasedby the timer 33 after the completion of the signal path by the switches36 and 37 The duration of the storage time, that is, the time duringwhich signals are stored in the memories 27 and 28 is t1 and correspondsto about one-fourth to one-half of the cycle duration of the highestfrequency. Usually, the duration of t1 will correspond to aboutthree-quarters of the cycle duration of the highest frequency. Thus, itis assured that the memories 27 and 28 are again ready for storing whenthe next minimum is reached, whereby said next minimum is stored untilit has been computed and passed on to the evaluating or regulatingmeans.

FIGS. 2 and 3 illustrate the wave form of a testing oscillation as itmay occur in a dynamic testing apparatus. A triangular oscillating waveform has been selected, for example. However, quite frequently, the loadoscillation may also have a sinusoidal wave form.

At the beginning of the oscillation the upper load OL follows the signalvoltage S. When the maximum M1 is reached the upper load 0L is stored inthe peak voltage storage or memory 27 as well as in the intermediatestorage or memory 28 in the form of a voltage OLsp. The peak voltagememory 27 or rather its content may be erased after the time t1 wherebythe memory 27 follows the signal voltage S until the next maximum M3,however, only if the signal voltage S exceeds the value which it hadsubsequently to the erasing of the memory 27 and the establishing of thesignal path. Where an intermediate memory 28 is employed the evaluationmay be accomplished during the two maxima M1 and M3.

If no intermediate memory 38 is used, the resulting wave form is shownin FIG. 3 also showing the signal voltage S and the upper load voltage0L and the lower load voltage UL. In the arrangement without theintermediate memory 28, the lowest value UL is first stored and theupper load OL follows the signal voltage S. During this time, a signalor voltage is applied to the upper input of the flip-flop 48 through theAND-gate 46, whereby a voltage appears at the output 54 of the flip-flop48. The trigger stage 42 flips after the maximum M1 has been passedwhereby a voltage is also applied to the conductor 53. Thus, theAND-gate 49 is actuated and triggers through the conductor 32 the timer33. After a short intermediate storage time which corresponds, forexample, to the time required by the computer 29, the switches 36 and 37are closed for a time duration corresponding to At whereby thedifference values AA and AM are supplied to the evaluating means 38 and39.

Instead of supplying the difference values AA and AM it is also possibleto supply the actual amplitude or mean load values to the evaluationdevices 38 and 39. After the completion of the time duration t1 thetimer 33 supplies an erasing control signal to the memory 27 whereby theupper load value as well as the lower load value are erased. Thereafterat the end of the erasing signal both values assume the value of thesignal voltage. As may beseen in FIG. 3, the lower load now follows thesignal voltage whereas the upper load assumes the instantaneous valueuntil the signal voltage exceeds such value. As soon as the minimum M2is exceeded, the lower load value UL is stored and a voltage is appliedto the lower input of the flip-flop 48 through the trigger stages 44 and45 as well as through the AND- gate 47. Thus, the flip-flop 48 assumesits opposite position and supplies a voltage to the output 55. Althoughthe invention has been described with reference to a specific exampleembodiment, it is to be understood, that it is intended to cover allmodifications and equivalents within the scope of the appended claims.

What is claimed is:

l. A peak value measuring and evaluating circuit atrangement forascertaining the maxima and minima of an oscillation represented by anelectrical signal comprising maximum and minimum value memory meanshaving an input to which said electrical signal is applied, said memorymeans further having first and second outputs and an erasing input,first and second evaluating means, controlled switching and circuitmeans for connecting said first and second memory outputs to therespective first and second evaluating means, a timer connected to saidcontrolled switching means and to said erasing input of said memorymeans, logic circuit means connected to said memory outputs and input toreceive appropriate trigger signals, and means for connecting said logiccircuit means to said timer, whereby said controlled switching means areclosed after the occurrence of an actual extreme value for a firstconstant evaluating time (At) during a second constant storage time(t1), said first constant time being independent of the frequency ofsaid oscillation, said second constant time (:1) corresponding at themost to one-half cycle duration of said oscillation, and whereby thecontent of said memory means is erased by said timer after the end ofsaid constant storage time.

2. The circuit arrangement according to claim 1, further comprising acomputer and comparator means, means for connecting said computer to theoutputs of said memory means for producing actual signal values, meansfor connecting said computer to said compara tor means, means forapplying rated signal values to said comparator means, and means forconnecting said comparator means to said controlled switching means,whereby said actual and rated signal values are compared by saidcomparator means for producing difference signals to be supplied to saidevaluating means through said controlled switching means.

3. The circuit arrangement according to claim 1, wherein said logiccircuit means comprise four trigger stages two each of which arecombined as pairs arranged for responding to a maximum value and to ainput connected to said timer.

3, 769, 594 Dated October 30, 19 73 Patent No.

Carl-Martin Wawra, et a1. Inventor(s) it is certified that error appearsin the above-identified patent and that said Letters Patent are herebycorrected as shown below:

On the cover sheet [73] Assignee: Carl Schenek Maschinenfabrik GmbH"should read Carl Schenck Maschinenfabrik GmbH insert [30] ForeignApplication Priority Data March 22, 1972 Germany P 22 13 736.6

Signed and sealed this 9th day of April 1974.

(SEAL) Attest:

EDWARD M.FLETCHER,JR. C. MARSHALL DANN Attesting Officer Commissioner ofPatents F ORM PO-105O (10-69) USCOMM'DC 50376-F'69 US. GOVERNMENTPRINTING OFFICE I969 0-386-334,

1. A peak value measuring and evaluating circuit arrangement forascertaining the maxima and minima of an oscillation represented by anelectrical signal comprising maximum and minimum value memory meanshaving an input to which said electrical signal is applied, said memorymeans further having first and second outputs and an erasing input,first and second evaluating means, controlled switching and circuitmeans for connecting said first and second memory outputs to therespective first and second evaluating means, a timer connected to saidcontrolled switching means and to said erasing input of said memorymeans, logic circuit means connected to said memory outputs and input toreceive appropriate trigger signals, and means for connecting said logiccircuit means to said timer, whereby said controlled switching means areclosed after the occurrence of an actual extreme value for a firstconstant evaluating time ( Delta t) during a second constant storagetime (t1), said first constant time being independent of the frequencyof said oscillation, said second constant time (t1) corresponding at themost to one-half cycle duration of said oscillation, and whereby thecontent of said memory means is erased by said timer after the end ofsaid constant storage time.
 2. The circuit arrangement according toclaim 1, further comprising a computer and comparator means, means forconnecting said computer to the outputs of said memory means forproducing actual signal values, means for connecting said computer tosaid comparator means, means for applying rated signal values to saidcomparator means, and means for connecting said comparator means to saidcontrolled switching means, whereby said actual and rated signal valuesare compared by said comparator means for producing difference signalsto be supplied to said evaluating means through said controlledswitching means.
 3. The circuit arrangement according to claim 1,wherein said logic circuit means comprise four trigger stages two eachof which are combined as pairs arranged for responding to a maximumvalue and to a minimum value respectively, negating AND-gate meansconnected to said pairs of trigger stages, flip-flop means connected tosaid negating AND-gate means, and an AND-gate connected to one of saidtrigger stages and to said flip-flop means as well as to said timer fortriggering the latter in response to a maximum or minimum value and inresponse to equality between said electrical signal and the storedsignal values.
 4. The circuit arrangement according to claim 1,comprising a further storage device connected in series with said memorymeans and also having an erasing input connected to said timer.